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ARM architecture

NameARM
DesignerARM Holdings
Bits32
Introduced1983
VersionARMv7
DesignRISC
TypeRegister-Register
EncodingFixed
BranchingCondition code
EndiannessBi (Little as default)
ExtensionsNEON, Thumb, Jazelle, VFP
Registers16

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The ARM is a 32-bit reduced instruction set computer (RISC) instruction set architecture (ISA) developed by ARM Holdings. It was known as the Advanced RISC Machine, and before that as the Acorn RISC Machine. The ARM architecture is the most widely used 32-bit ISA in terms of numbers produced. They were originally conceived as a processor for desktop personal computers by Acorn Computers, a market now dominated by the x86 family used by IBM PC compatible and Apple Macintosh computers. The relative simplicity of ARM processors made them suitable for low power applications. This has made them dominant in the mobile and embedded electronics market, as relatively low cost, and small microprocessors and microcontrollers.

In 2005, about 98 percent of the more than one billion mobile phones sold each year used at least one ARM processor. , ARM processors account for approximately 90% of all embedded 32-bit RISC processors. ARM processors are used extensively in consumer electronics, including PDAs, mobile phones, digital media and music players, hand-held game consoles, calculators and computer peripherals such as hard drives and routers.

The ARM architecture is licensable. Companies that are current or former ARM licensees include Alcatel-Lucent, Apple Inc., Atmel, Broadcom, Cirrus Logic, Digital Equipment Corporation, Freescale, Intel (through DEC), LG, Marvell Technology Group, Microsoft, NEC, Nuvoton, Nvidia, NXP (previously Philips), Oki, Qualcomm, Samsung, Sharp, STMicroelectronics, Symbios Logic, Texas Instruments, VLSI Technology, Yamaha and ZiiLABS.

ARM processors are developed by ARM and by ARM licensees. Prominent ARM processor families developed by ARM Holdings include the ARM7, ARM9, ARM11 and Cortex. Notable ARM processors developed by licensees include DEC StrongARM, Freescale i.MX, Marvell (formerly Intel) XScale, Nintendo, Nvidia Tegra, ST-Ericsson Nomadik, Qualcomm Snapdragon, the Texas Instruments OMAP product line, the Samsung Hummingbird and the Apple A4.

ARM architecture Video

OCOSMOS MIP(Multimedia Internet Phone) OCS5 Intro Video. OCS5 Based on ARM 7th Generation Architecture & Google Android OS. (Record : Acrofan)
2.15 min. | 5.0 user rating		 OCOSMOS MIP(Multimedia Internet Phone) OCS5 Korean Language Input Demo. OCS5 Based on ARM 7th Generation Architecture & Google Android OS. (Record : Acrofan)
0.75 min. | 0 user rating		 OCOSMOS MIP(Multimedia Internet Phone) OCS5 Using Activity Demo. OCS5 Based on ARM 7th Generation Architecture & Google Android OS. (Record : Acrofan)
3.57 min. | 0 user rating		 OCOSMOS Cubic type Folder shell Program 'CUBE' Intro Video. OCS5 Based on ARM 7th Generation Architecture & Google Android OS. (Record : Acrofan)
1.73 min. | 5.0 user rating		 OCOSMOS MIP(Multimedia Internet Phone) OCS5 Applications & Service Demo. OCS5 Based on ARM 7th Generation Architecture & Google Android OS. (Record : Acrofan)
4.28 min. | 0 user rating
OCOSMOS MIP(Multimedia Internet Phone) OCS7 Intro Video. OCS5 Based on ARM Next Generation Architecture & Google Android OS. (Record : Acrofan)
0.72 min. | 0 user rating		 OCOSMOS Obar control Demo. Blizzard Entertainment Starcraft Play Demo. OCS5 Based on ARM 7th Generation Architecture & Google Android OS. (Record : Acrofan)
0.72 min. | 0 user rating		 OCOSMOS MIP(Multimedia Internet Phone) OCS5 Japanese Language Input Demo. OCS5 Based on ARM 7th Generation Architecture & Google Android OS. (Record : Acrofan)
0.60 min. | 5.0 user rating		 OCOSMOS Obar control Demo. OCOSMOS's choice is Google Maps. OCS5 Based on ARM 7th Generation Architecture & Google Android OS. (Record : Acrofan)
1.80 min. | 0 user rating		 OCOSMOS MIP(Multimedia Internet Phone) OCS5 Chinese Language Input Demo. OCS5 Based on ARM 7th Generation Architecture & Google Android OS. (Record : Acrofan)
0.60 min. | 5.0 user rating

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Seventh Iteration of Android Rumored to Be Called “Ice Cream” - Erictric Tweet this news
Erictric--The information was leaked by ARM Holdings President Tudor Brown, who has extensive knowledge of the Android roadmap due to the use of the -ARM architecture- ... - Date : Sat, 16 Oct 2010 00:50:41 GMT+00:00
Acer to announce tablet range - MobileShop.com (blog) Tweet this news
MobileShop.com (blog)--Previous rumours have stated the tablets will have a seven and a ten-inch screen, run on Android, have 3G support and -ARM architecture-. ... - Date : Fri, 29 Oct 2010 11:51:25 GMT+00:00
Nook Color uses ARM A8 and follows Apple's application model - High Tech Lounge Tweet this news
High Tech Lounge--The clock speed has not been mentioned, but it was described as -ARM- Cortex-A8 -architecture-, which means the speed is near that of the iPad o other ... - Date : Sun, 31 Oct 2010 22:05:39 GMT+00:00
Lenovo to Release Enterprise Tablets - Softpedia Tweet this news
Softpedia--Even the other models so far unveiled have focused on a combination of the -ARM architecture- on the hardware side, and the Android OS on the software side. ... - Date : Mon, 18 Oct 2010 15:17:54 GMT+00:00
Intel readying iPhone app conversion tool - HEXUS Tweet this news
HEXUS--In an interview with IDG, Intel VP Doug Fisher revealed that the company was working on a tool to help port apps written for the -ARM architecture- - and ... - Date : Thu, 07 Oct 2010 11:19:38 GMT+00:00
Will Windows8 Use ARM? - Windows 8 News Tweet this news
Windows 8 News--The manufacturer and developer is by ARM Holdings. The -ARM architecture- is a widely used 32-bit ISA based on the numbers produced. ... - Date : Fri, 15 Oct 2010 23:41:43 GMT+00:00
China Claims Fastest-Ever Supercomputer, Topping US - NewsFactor Network Tweet this news
NewsFactor Network--Tianhe-1A is the world's fastest supercomputer, China says, taking the title from the US The x86 -ARM architecture- Tianhe can do more ... - Date : Thu, 28 Oct 2010 18:40:38 GMT+00:00
ARM Heads From Smartphones To Servers And Your Microwave - Forbes (blog) Tweet this news
Forbes (blog)--ARM wants to design them; Image via Wikipedia It's been designing the chips that go in our phones since the 1990s, and -ARM's architecture- continues to ... - Date : Wed, 27 Oct 2010 09:28:00 GMT+00:00

Licensing growth :
ARM Family ARM Architecture ARM Core Feature Cache (I/D), MMU Typical MIPS @ MHz
ARM1 ARMv1 ARM1 First implementation None
ARM2 ARMv2 ARM2 ARMv2 added the MUL (multiply) instruction None 4 MIPS @ 8 MHz
0.33 DMIPS/MHz
ARMv2a ARM250 Integrated MEMC (MMU), Graphics and IO processor. ARMv2a added the SWP and SWPB (swap) instructions. None, MEMC1a 7 MIPS @ 12 MHz
ARM3 ARMv2a ARM3 First integrated memory cache. 4 KB unified 12 MIPS @ 25 MHz
0.50 DMIPS/MHz
ARM6 ARMv3 ARM60 ARMv3 first to support 32-bit memory address space (previously 26-bit) None 10 MIPS @ 12 MHz
ARM600 As ARM60, cache and coprocessor bus (for FPA10 floating-point unit). 4 KB unified 28 MIPS @ 33 MHz
ARM610 As ARM60, cache, no coprocessor bus. 4 KB unified 17 MIPS @ 20 MHz
0.65 DMIPS/MHz
ARM7 ARMv3 ARM700 8 KB unified 40 MHz
ARM710 As ARM700, no coprocessor bus. 8 KB unified 40 MHz
ARM710a As ARM710 8 KB unified 40 MHz
0.68 DMIPS/MHz
ARM7TDMI ARMv4T ARM7TDMI(-S) 3-stage pipeline, Thumb none 15 MIPS @ 16.8 MHz
63 DMIPS @ 70 MHz
ARM710T As ARM7TDMI, cache 8 KB unified, MMU 36 MIPS @ 40 MHz
ARM720T As ARM7TDMI, cache 8 KB unified, MMU with Fast Context Switch Extension 60 MIPS @ 59.8 MHz
ARM740T As ARM7TDMI, cache MPU
ARM7EJ ARMv5TEJ ARM7EJ-S 5-stage pipeline, Thumb, Jazelle DBX, Enhanced DSP instructions none
ARM8 ARMv4 ARM810 5-stage pipeline, static branch prediction, double-bandwidth memory 8 KB unified, MMU 84 MIPS @ 72 MHz
1.16 DMIPS/MHz
StrongARM ARMv4 SA-1 5-stage pipeline 16 KB/8 � 16 KB, MMU 203 � 206 MHz
1.0 DMIPS/MHz
ARM9TDMI ARMv4T ARM9TDMI 5-stage pipeline, Thumb none
ARM920T As ARM9TDMI, cache 16 KB/16 KB, MMU with FCSE (Fast Context Switch Extension) 200 MIPS @ 180 MHz
ARM922T As ARM9TDMI, caches 8 KB/8 KB, MMU
ARM940T As ARM9TDMI, caches 4 KB/4 KB, MPU
ARM9E ARMv5TE ARM946E-S Thumb, Enhanced DSP instructions, caches variable, tightly coupled memories, MPU
ARM966E-S Thumb, Enhanced DSP instructions no cache, TCMs
ARM968E-S As ARM966E-S no cache, TCMs
ARMv5TEJ ARM926EJ-S Thumb, Jazelle DBX, Enhanced DSP instructions variable, TCMs, MMU 220 MIPS @ 200 MHz,
ARMv5TE ARM996HS Clockless processor, as ARM966E-S no caches, TCMs, MPU
ARM10E ARMv5TE ARM1020E 6-stage pipeline, Thumb, Enhanced DSP instructions, (VFP) 32 KB/32 KB, MMU
ARM1022E As ARM1020E 16 KB/16 KB, MMU
ARMv5TEJ ARM1026EJ-S Thumb, Jazelle DBX, Enhanced DSP instructions, (VFP) variable, MMU or MPU
XScale ARMv5TE XScale 7-stage pipeline, Thumb, Enhanced DSP instructions 32 KB/32 KB, MMU 133 � 400 MHz
Bulverde Wireless MMX, Wireless SpeedStep added 32 KB/32 KB, MMU 312 � 624 MHz
Monahans Wireless MMX2 added 32 KB/32 KB (L1), optional L2 cache up to 512 KB, MMU up to 1.25 GHz
ARM11 ARMv6 ARM1136J(F)-S 8-stage pipeline, SIMD, Thumb, Jazelle DBX, (VFP), Enhanced DSP instructions variable, MMU 740 @ 532 � 665 MHz (i.MX31 SoC), 400 � 528 MHz
ARMv6T2 ARM1156T2(F)-S 8-stage pipeline, SIMD, Thumb-2, (VFP), Enhanced DSP instructions variable, MPU
ARMv6ZK ARM1176JZ(F)-S As ARM1136EJ(F)-S variable, MMU + TrustZone 965 DMIPS @ 772 MHz, up to 2 600 DMIPS with four processors
ARMv6K ARM11 MPCore As ARM1136EJ(F)-S, 1 � 4 core SMP variable, MMU
Cortex-A ARMv7-A Cortex-A5 (MPCore) Application profile, ARM / Thumb / Thumb-2 / DSP / SIMD / Optional VFPv3 FPU / Optional NEON / Jazelle RCT and DBX, 1 � 4 cores / optional MPCore, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP) 4-64KB / 4-64KB L1, MMU + TrustZone 1.57 DMIPS / MHz per core
Cortex-A8 Application profile, ARM / Thumb / Thumb-2 / VFPv3 FPU / Optional NEON / Jazelle RCT and DAC, 13-stage superscalar pipeline 16-32KB / 16-32KB L1, 0-1MB L2 opt ECC, MMU + TrustZone up to 2 000 (2.0 DMIPS/MHz in speed from 600 MHz to greater than 1 GHz)
Cortex-A9 MPCore Application profile, ARM / Thumb / Thumb-2 / DSP / Optional VFPv3 FPU / Optional NEON / Jazelle RCT and DBX, out-of-order speculative issue superscalar, 1 � 4 SMP cores, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP) 16-64KB / 16-64KB L1, 0-8MB L2 opt Parity, MMU + TrustZone 2.5 DMIPS/MHz per core, 10 000 DMIPS @ 2 GHz on Performance Optimized TSMC 40G (dual core)
Cortex-A15 MPCore Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / Jazelle RCT and DBX / Hardware virtualization, out-of-order speculative issue superscalar, 1 � 4 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP 32KB / 32KB L1, 0-4MB L2, L1 & L2 have Parity & ECC, MMU + TrustZone
Cortex-R ARMv7-R Cortex-R4 Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lockstep with fault logic 0-64KB / 0-64KB, 0-2 of 0-8MB TCM, opt MPU with 8/12 regions
Cortex-R5 (MPCore) Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lock-step with fault logic / optional as 2 independent cores, low-latency peripheral port (LLPP), accelerator coherency port (ACP) 0-64KB / 0-64KB, 0-2 of 0-8MB TCM, opt MPU with 12/16 regions
Cortex-R7 (MPCore) Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, optional parity & ECC for internal buses / cache / TCM, 11-stage pipeline dual-core running lock-step with fault logic / out-of-order execution / dynamic register renaming / optional as 2 independent cores, low-latency peripheral port (LLPP), ACP 0-64KB / 0-64KB, ? of 0-128KB TCM, opt MPU with 16 regions
Cortex-M ARMv6-M Cortex-M0 Microcontroller profile, Thumb + Thumb-2 subset (BL, MRS, MSR, ISB, DSB, DMB), hardware multiply instruction, optional system timer, no bit-banding memory No cache, No TCM, No MPU 0.9 DMIPS/MHz
Cortex-M1 Microcontroller profile, Thumb + Thumb-2 subset (BL, MRS, MSR, ISB, DSB, DMB), hardware multiply instruction (optional small), OS option adds SVC / banked stack pointer / system timer, no bit-banding memory No cache, 0-1024KB I-TCM, 0-1024KB D-TCM, No MPU 136 DMIPS @ 170 MHz, (0.8 DMIPS/MHz FPGA-dependent)
ARMv7-M Cortex-M3 Microcontroller profile, Thumb / Thumb-2, hardware multiply and divide instructions, optional bit-banding memory No cache, No TCM, opt MPU with 8 regions 125 DMIPS @ 100 MHz
ARMv7-ME Cortex-M4 Microcontroller profile, Thumb / Thumb-2 / DSP / optional FPv4 single-precision FPU, hardware multiply and divide instructions, optional bit-banding memory No cache, No TCM, opt MPU with 8 regions 1.25 DMIPS/MHz
ARM Family ARM Architecture ARM Core Feature Cache (I/D), MMU Typical MIPS @ MHz

Licensing growth :
ARM Core Devices Products
ARM1 ARM1 ARM Evaluation System second processor for BBC Micro
ARM2 ARM2 Acorn Archimedes, Chessmachine
ARM250 ARM250 Acorn Archimedes
ARM3 ARM3 Acorn Archimedes
ARM60 ARM60 3DO Interactive Multiplayer, Zarlink GPS Receiver
ARM610 ARM610 Acorn Risc PC 600, Apple Newton 100 series
ARM700 ARM700 Acorn Risc PC prototype CPU card
ARM710 ARM710 Acorn Risc PC 700
ARM710a ARM7100, ARM 7500 and ARM7500FE Acorn Risc PC 700, Apple eMate 300, Psion Series 5 (ARM7100), Acorn A7000 (ARM7500), Acorn A7000+ (ARM7500FE), Network Computer (ARM7500FE)
ARM7TDMI(-S) Atmel AT91SAM7, NXP Semiconductors LPC2000 and LH754xx, Actel CoreMP7 Game Boy Advance, Nintendo DS, Apple iPod, Lego NXT, Juice Box, Garmin Navigation Devices (1990s � early 2000s)
ARM710T Psion Series 5mx, Psion Revo/Revo Plus/Diamond Mako
ARM720T NXP Semiconductors LH7952x Zipit Wireless Messenger
StrongARM Digital SA-110, SA-1100, SA-1110
ARM810 Acorn Risc PC prototype CPU card
ARM920T Atmel AT91RM9200, AT91SAM9, Cirrus Logic EP9302, EP9307, EP9312, EP9315, Samsung S3C2442 and S3C2410 Armadillo, GP32, GP2X (first core), Tapwave Zodiac (Motorola i.MX1), Hewlett-Packard HP-49/50 Calculators, Sun SPOT, HTC TyTN, FIC Neo FreeRunner), Garmin Navigation Devices (mid � late 2000s), TomTom navigation devices
ARM922T NXP Semiconductors LH7A40x
ARM940T GP2X (second core), Meizu M6 Mini Player
ARM926EJ-S Texas Instruments OMAP1710, OMAP1610, OMAP1611, OMAP1612, OMAP-L137, OMAP-L138; Qualcomm MSM6100, MSM6125, MSM6225, MSM6245, MSM6250, MSM6255A, MSM6260, MSM6275, MSM6280, MSM6300, MSM6500, MSM6800; Freescale i.MX21, i.MX27, i.MX28, Atmel AT91SAM9, NXP Semiconductors, Samsung S3C2412 LPC30xx, NEC C10046F5-211-PN2-A SoC � undocumented core in the ATi Hollywood graphics chip used in the Wii, Telechips TCC7801, TCC7901, ZiiLABS ZMS-05, Rockchip RK2806 and RK2808, NeoMagic MiMagic Family MM6, MM6+, MM8, MTV. Mobile phones: Sony Ericsson (K, W series); Siemens and Benq (x65 series and newer); LG Arena; GPH Wiz; Squeezebox Duet Controller (Samsung S3C2412). Squeezebox Radio; Buffalo TeraStation Live (NAS); Drobo FS (NAS); Western Digital MyBook I World Edition; Western Digital MyBook II World Edition; Seagate FreeAgent DockStar STDSD10G-RK; Seagate FreeAgent GoFlex Home; Chumby Classic
ARM946E-S Nintendo DS, Nokia N-Gage, Canon PowerShot A470, Canon EOS 5D Mark II, Conexant 802.11 chips, Samsung S5L2010
ARM966E-S STMicroelectronics STR91xF
ARM968E-S NXP Semiconductors LPC29xx
ARM1026EJ-S Conexant so4610 and so4615 ADSL SoC
XScale Intel 80200, 80219, PXA210, PXA250, PXA255, PXA263, PXA26x, PXA27x, PXA3xx, PXA900, IXC1100, IXP42x
ARM1136J(F)-S Texas Instruments OMAP2420, Qualcomm MSM7200, MSM7201A, MSM7227, Freescale i.MX31 and MXC300-30
ARM1176JZ(F)-S Conexant CX2427X, Nvidia GoForce 6100; Telechips TCC9101, TCC9201, TCC8900, Fujitsu MB86H60, Samsung S3C6410, S3C6430, Qualcomm MSM7627, Infineon X-GOLD 213 Apple iPhone (original and 3G), Apple iPod touch (1st and 2nd Generation), Motorola RIZR Z8, Motorola RIZR Z10, Nintendo 3DS
ARM11 MPCore Nvidia APX 2500 (Tegra)
Cortex-A8 Texas Instruments OMAP3xxx series, FreeScale i.MX51-SOC, Apple A4, ZiiLABS ZMS-08, Samsung Hummingbird S5PC100/S5PC110 , Qualcomm Snapdragon QSD8x50(A)/MSM7x30/MSM8255, Marvell ARMADA 500/600, Rockchip RK2918 HTC Desire, SBM7000, Oregon State University OSWALD, Gumstix Overo Earth, Pandora, Apple iPhone 3GS, Apple iPod touch (3rd and 4th Generation), Apple iPad (A4), Apple iPhone 4 (A4), Apple TV (Second Generation) (A4), Archos 5, BeagleBoard, Genesi EFIKA MX, Motorola Droid, Motorola Droid X, Motorola Droid 2, Motorola Droid R2D2 Edition, Palm Pre, Palm Pre 2 , HP TouchPad, HP Veer, HP Pre 3, Samsung Omnia HD, Samsung Wave S8500, Samsung i9000 Galaxy S, Samsung P1000 Galaxy Tab, Sony Ericsson Satio, Sony Ericsson Xperia X10, Touch Book, Nokia N900, Meizu M9, Google Nexus S, Sharp PC-Z1 "Netwalker".
Cortex-A9 Texas Instruments OMAP4430/4440, ST-Ericsson U8500 / U5500, Nvidia Tegra2, Qualcomm Snapdragon QSD8672/MSM8260/MSM8660, Samsung Orion, STMicroelectronics SPEAr1310, Xilinx Extensible Processing Platform, Trident PNX847x/8x/9x STB SoC, Freescale i.MX6 Apple iPad 2 (A5), LG Optimus 2X, Motorola Atrix 4G, Motorola DROID BIONIC, Motorola Xoom, PandaBoard, NGP(PSP2)
Cortex-A15 Qualcomm Snapdragon MSM8270/MSM8960, Texas Instruments OMAP5, Samsung, ST Ericsson, Nvidia
Cortex-R4(F) Broadcom, Texas Instruments TMS570
Cortex-M0 NXP Semiconductors LPC11xx, Triad Semiconductor, Melfas, Chungbuk Technopark, Nuvoton, austriamicrosystems, Rohm
Cortex-M1 devices, III, other FPGA products are also supported e.g. Synplicity
Cortex-M3 Texas Instruments Stellaris, STMicroelectronics STM32, NXP Semiconductors LPC17xx, Toshiba TMPM330, Ember EM3xx, Atmel AT91SAM3, Europe Technologies EasyBCU, Energy Micro EFM32, Actel SmartFusion, mbed microcontroller
Cortex-M4 Freescale Kinetis, NXP Semiconductors LPC43xx, STMicroelectronics
ARM Core Devices Products



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